1. Field
Various embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor device which performs an error correction code (ECC) operation.
2. Description of the Related Art
After semiconductor memory devices are fabricated, a test is performed to screen for failures, for example, failed memory cells. Column address information corresponding to the failed memory cells is stored in a storage unit. The semiconductor memory devices perform an ECC operation to correct errors in data. When the semiconductor memory devices have a failed column, an ECC operation is not performed on the failed column.
When a semiconductor memory device performs an ECC operation on column lines, the semiconductor memory device may not perform the ECC operation on all of the columns lines at one time, but perform an ECC operation on a group column lines. An ECC operation performed on a group of column lines is referred to as a unit ECC operation. Conventionally, the number of column lines in a unit ECC operation had been set as a fixed value. Therefore, when there was a failed column within a group, the semiconductor memory device ignored the failed column line and performs an ECC operation on the remaining column lines. Thus, when failed column lines were within the group, the number of valid column lines on which the ECC operation was performed was reduced by the number of failed column lines. For example, when a group for a unit ECC operation has 1024 bytes of column lines and 3 bytes of failed column lines, valid column lines may be reduced to 1021 bytes, thereby degrading the efficiency of ECC operations.